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| Features * High Performance, Low Power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture - 124 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 8 MIPS Throughput at 8 MHz High Endurance Non-volatile Memory Segments - 16K/32K Bytes of In-System Self-Programmable Flash (ATmega16HVB/32HVB) - 512/1K Bytes EEPROM - 1K/2K Bytes Internal SRAM - Write/Erase Cycles 10,000 Flash/100,000 EEPROM - Data retention: 20 years at 85C/100 years at 25C(1) - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - Programming Lock for Software Security Battery Management Features - Two, three or Four Cells in Series - High-current Protection (Charge and Discharge) - Over-current Protection (Charge and Discharge) - Short-circuit Protection (Discharge) - High Voltage Outputs to Drive N-Channel Charge/Discharge FETs - High Voltage Output to drive P-Channel Precharge FET - Integrated Cell Balancing FETs Peripheral Features - Two configurable 8- or 16-bit Timers with Separate Prescaler, Optional Input Capture (IC), Compare Mode and CTC - SPI - Serial Programmable Interface - 12-bit Voltage ADC, Six External and One Internal ADC Input - High Resolution Coulomb Counter ADC for Current Measurements - TWI Serial Interface for SM-Bus - Programmable Watchdog Timer Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI ports - Power-on Reset - On-chip Voltage Regulator with Short-circuit Monitoring Interface - External and Internal Interrupt Sources - Sleep Modes: Idle, ADC Noise Reduction, Power-save, and Power-off Additional Secure Authentication Features available only under NDA Packages - 44-lead TSSOP Operating Voltage: 4 - 25V Maximum Withstand Voltage (High-voltage pins): 35V Temperature Range: -30C to 85C Speed Grade: 1-8 MHz * * 8-bit Microcontroller with 16K/32K Bytes In-System Programmable Flash ATmega16HVB ATmega32HVB Advance Information Summary * * * * * * * * 8042AS-AVR-09/08 1. Pin Configurations 1.1 TSSOP Figure 1-1. TSSOP - pinout ATmega16HVB/32HVB NI NNI VREFGND VREF GND VREG PA0(ADC0/SGND/PCINT0) PA1(ADC1/SGND/PCINT1) PA2(PCINT2/T0) PA3(PCINT3/T1) NC VFET BATT VCC GND OD NC OC RESET/dw PB0(PCINT4/ICP00) PB1(PCINT5/CKOUT) PB2(PCINT6) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 PI PPI NV PV1 PV2 PV3 PV4 PVT VCC GND PC5 PC4(SCL) PC3(INT3/SDA) PC2(INT2) PC1(INT1) PC0(INTO/EXTPROT) PB7(MISO/PCINT11) NC PB6(MOSI/PCINT10) PB5(SCK/PCINT9) PB4(SS/PCINT8) PB3(PCINT7) 1.2 Pin Descriptions 1.2.1 VFET High voltage supply pin. This pin is used as supply for the internal voltage regulator, described in "Voltage Regulator" on page 132. 1.2.2 VCC Digital supply voltage. Normally connected to VREG. 1.2.3 VREG Output from the internal Voltage Regulator. Used for external decoupling to ensure stable regulator operation. For details, see "Voltage Regulator" on page 132. 2 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB 1.2.4 VREF Internal Voltage Reference for external decoupling. For details, see "Voltage Reference and Temperature Sensor" on page 124. 1.2.5 VREFGND Ground for decoupling of Internal Voltage Reference. For details, see "Voltage Reference and Temperature Sensor" on page 124. Do not connect to GND or SGND on PCB. 1.2.6 GND Ground 1.2.7 Port A (PA3..PA0) Port A serves as a low-voltage 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega16HVB/32HVB as listed in "Alternate Functions of Port A" on page 76. 1.2.8 Port B (PB7..PB0) Port B is a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16HVB/32HVB as listed in "Alternate Functions of Port B" on page 77. 1.2.9 Port C (PC5) Port C (PC5) is a high voltage Open Drain output port. Port C serves the functions of various special features of the ATmega16HVB/32HVB as listed in "Alternate Functions of Port C" on page 67. 1.2.10 Port C (PC4..PC0) Port C is a 5-bit high voltage Open Drain bi-directional I/O port. Port C serves the functions of various special features of the ATmega16HVB/32HVB as listed in "Alternate Functions of Port C" on page 67. 1.2.11 OC/OD High voltage output to drive Charge/Discharge. For details, see "FET Driver" on page 147. 1.2.12 PI/NI Filtered positive/negative input from external current sense resistor, used to by the Coulomb Counter ADC to measure charge/discharge currents flowing in the battery pack. For details, see "Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC" on page 110. 3 8042AS-AVR-09/08 1.2.13 PPI/NNI Unfiltered positive/negative input from external current sense resistor, used by the battery protection circuit, for over-current and short-circuit detection. For details, see "Battery Protection" on page 135. 1.2.14 NV/PV1/PV2/PV3/PV4 NV, PV1, PV2, PV3, and PV4 are the inputs for battery cells 1, 2, 3 and 4, used by the Voltage ADC to measure each cell voltage. For details, see "Voltage ADC - 7-channel General Purpose 12-bit Sigma-Delta ADC" on page 118. 1.2.15 PVT Defines the source voltage level for the Charge FET driver. For details, see "FET Driver" on page 147. 1.2.16 BATT Input for detecting when a charger is connected. Defines the source voltage level for the Discharge FET driver. For details, see "FET Driver" on page 147. 1.2.17 RESET/dw Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page 38. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE communication pin. 4 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB 2. Overview The ATmega16HVB/32HVB is a monitoring and protection circuit for 3 and 4-cell Li-ion applications with focus on high security/authentication, low cost and high utilization of the cell energy. The device contains secure authentication features as well as autonomous battery protection during charging and discharging. The External Protection Input can be used to implement other battery protection mechanisms using external components, e.g. protection against chargers with too high charge voltage can be easily implemented with a few low cost passive components. The feature set makes the ATmega16HVB/32HVB a key component in any system focusing on high security, battery protection, high system utilization and low cost. Figure 2-1. Block Diagram PB7..0 PC5..0 PB0 Oscillator Circuits / Clock Generation Oscillator Sampling Interface SPI VCC Watchdog Timer Flash SRAM 8/16-bit T/C1 Voltage ADC TWI 8/16-bit T/C0 FET Control OC OD OPC PPI NNI PV4 PV3 PV2 PV1 NV PORTB (8) PORTC (6) Watchdog Oscillator Current Protection Cell Balancing RESET/dW Power Supervision POR & RESET Program Logic debugWIRE VPTAT CPU EEPROM Voltage Reference VREF VREFGND PI NI GND BATT Charger Detect Security Module DATA BUS Coulumb Counter ADC VFET VREG Voltage Regulator Voltage Regulator Monitor Interface PORTA (4) PA1..0 PA3..0 ATmega16HVB/32HVB provides the necessary redundancy on-chip to make sure that the battery is protected in critical failure modes. The chip is specifically designed to provide safety for the battery cells in case of pin shorting, loss of power (either caused by battery pack short or VCC 5 8042AS-AVR-09/08 short), illegal charger connection or software runaway. This makes ATmega16HVB/32HVB the ideal 1-chip solution for applications with focus on high safety. The ATmega16HVB/32HVB features an integrated voltage regulator that operates at a wide range of input voltages, 4 - 25 volts. This voltage is regulated to a constant supply voltage of nominally 3.3 volts for the integrated logic and analog functions. The regulator capabilities, combined with a extremely low power consumption in the power saving modes, greatly enhances the cell energy utilization compared to existing solutions. The chip utilizes Atmel's patented Deep Under-voltage Recovery (DUVR) mode that supports pre-charging of deeply discharged battery cells without using a separate Pre-charge FET. Optionally, Pre-charge FETs are supported for integration into many existing battery charging schemes. The battery protection monitors the charge and discharge current to detect illegal conditions and protect the battery from these when required. A 12-bit Voltage ADC allows software to monitor each cell voltage individually with high accuracy. The ADC also provides one internal input channel to measure on-chip temperature and two input channels intended for external thermistors. An 18-bit ADC optimized for Coulomb Counting accumulates charge and discharge currents and reports accumulated current with high resolution and accuracy. It can also be used to provide instantaneous current measurements with 13 bit resolution. Integrated Cell Balancing FETs allow cell balancing algorithms to be implemented in software. The MCU provides the following features: 16K/32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K bytes EEPROM, 1K/2K bytes SRAM. 32 general purpose working registers, 12 general purpose I/O lines, 5 general purpose high voltage open drain I/O lines, one general purpose super high voltage open drain output, debugWIRE for On-chip debugging and SPI for In-system Programming, a SM-Bus compliant TWI module, two flexible Timer/Counters with Input Capture and compare modes. Internal and external interrupts, a 12-bit Sigma Delta ADC for voltage and temperature measurements, a high resolution Sigma Delta ADC for Coulomb Counting and instantaneous current measurements, integrated cell balancing FETs, Additional Secure Authentication Features, an autonomous Battery Protection module, a programmable Watchdog Timer with internal Oscillator, and software selectable power saving modes. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The device is manufactured using Atmel's high voltage high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, through an SPI serial interface, by a conventional non-volatile memory programmer or by an Onchip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true ReadWhile-Write operation. By combining an 8-bit RISC CPU with In-System Self-ProgrammableFlash and highly accurate analog front-end in a monolithic chip. The Atmel ATmega16HVB/32HVB is a powerful microcontroller that provides a highly flexible and cost effective solution. It is part of the AVR Smart Battery family that provides secure 6 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB authentication, highly accurate monitoring and autonomous protection for Lithium-ion battery cells. The ATmega16HVB/32HVB AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Onchip Debugger. 2.1 Comparison Between ATmega16HVB and ATmega32HVB The ATmega16HVB and ATmega32HVB differ only in memory size for Flash, EEPROM and internal SRAM. Table 2-1 summarizes the different configuration for the two devices. Table 2-1. Configuration summary Device ATmega16HVB ATmega32HVB Flash 16K 32K EEPROM 512 1K SRAM 1K 2K 3. Disclaimer All Min, Typ and Max values contained in this datasheet are preliminary estimates based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Final values will be available after the device is characterized. 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.n1 Note: 1. 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. 7 8042AS-AVR-09/08 6. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) Name Reserved BPPLR BPCR BPHCTR BPOCTR BPSCTR BPCHCD BPDHCD BPCOCD BPDOCD BPSCD Reserved BPIFR BPIMSK CBCR FCSR Reserved Reserved Reserved Reserved Reserved CADRDC CADRCC CADCSRC CADCSRB CADCSRA CADICH CADICL CADAC3 CADAC2 CADAC1 CADAC0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CHGDCSR Reserved BGCSR BGCRR BGCCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved ROCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 - - - - - - Bit 6 - - - - - Bit 5 - - EPID Bit 4 - - SCD Bit 3 - - DOCD Bit 2 - - COCD HCPT[5:0] OCPT[5:0] Bit 1 - BPPLE DHCD Bit 0 - BPPL CHCD Page 140 141 142 142 142 145 144 144 143 143 SCPT[6:0] CHCDL[7:0] DHCDL[7:0] COCDL[7:0] DOCDL[7:0] SCDL[7:0] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCIF SCIE - - - - - - - CADRDC[7:0] CADRCC[7:0] - DOCIF DOCIE CBE4 DUVRD - - - - - - COCIF COCIE CBE3 CPS - - - - - - DHCIF DHCIE CBE2 DFE - - - - - - CHCIF CHCIE CBE1 CFE - - - - - 117 116 146 145 153 150 - CADEN CADACIE CADPOL CADRCIE CADUB CADICIE CADAS[1:0] CADIC[15:8] CADIC[7:0] - CADACIF CADSI[1:0] CADRCIF CADVSE CADICIF CADSE 115 114 113 115 115 116 116 116 116 CADAC[31:24] CADAC[23:16] CADAC[15:8] CADAC[7:0] - - - - - - - - - - - - - - - - - - - - - - ROCS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ROCD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BGD - - - - - - - - - - - BATTPVL - BGSCDE BGCR[7:0] BGCC[5:0] - - - - - - - - - - - - - - - - - - - - - - - ROCWIF - - - - - - - - - - - - - - - ROCWIE - - - - - - - - - - - - - - - - - - - CHGDISC1 - - - - - - - - - - - - - CHGDISC1 - - - - - - - - - - - - - CHGDIF - BGSCDIF - - - - - - - - - - - CHGDIE - BGSCDIE 131 127 126 240 134 8 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB Address (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) Name Reserved TWBCSR TWAMR TWCR TWDR TWAR TWSR TWBR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1B OCR1A Reserved Reserved TCNT1H TCNT1L Reserved Reserved TCCR1B TCCR1A Reserved DIDR0 Bit 7 - TWBCIF TWINT Bit 6 - TWBCIE TWEA Bit 5 - - TWSTA Bit 4 - - TWAM[6:0] TWSTO TWA[6:0] Bit 3 - - TWWC Bit 2 - TWBDT1 TWEN Bit 1 - TWBDT0 - Bit 0 - TWBCIP - TWIE TWGCE Page 185 185 182 184 184 183 182 2-wire Serial Interface Data Register TWS[7:3] 2-wire Serial Interface Bit Rate Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TWPS1 TWPS0 Timer/Counter1 - Output Compare Register B Timer/Counter1 - Output Compare Register A - - - - - - - - - - - - - - - - 97 97 Timer/Counter1 (8 Bit) High Byte Timer/Counter1 (8 Bit) Low Byte - - - TCW1 - - - - - ICEN1 - - - - - ICNC1 - - - - - ICES1 - - - - - ICS1 - - - - CS12 - - - - - CS11 - - PA1DID - - CS10 WGM10 - PA0DID 97 97 83 96 123 9 8042AS-AVR-09/08 Address (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) Name Reserved VADMUX Reserved VADCSR VADCH VADCL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 Reserved PCMSK1 PCMSK0 Reserved EICRA PCICR Reserved FOSCCAL Reserved PRR0 Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved DWDR Reserved Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 OCR0B OCR0A TCNT0H TCNT0L TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Bit 7 - - - - - - - - - - - - - - - - - - ISC31 - - - - - - CLKPCE WDIF I SP15 SP7 - - - - - - - - - - - - - SPIF SPIE Bit 6 - - - - - - - - - - - - - - - - - - ISC30 - - - PRTWI - - - WDIE T SP14 SP6 - - - - - - - - - - - - - WCOL SPE Bit 5 - - - - - - - - - - - - - - - - - - ISC21 - - - PRVRM - - - WDP3 H SP13 SP5 - - - - - SIGRD - CKOE - - - - - - DORD Bit 4 - - - - - Bit 3 - - VADEN Bit 2 - Bit 1 - Bit 0 - Page 121 VADMUX[3:0] - VADSC - VADCCIF - VADCCIE 121 122 122 VADC Data Register High byte - - - - - - - - ICIE1 ICIE0 - PCINT[15:8] - - - - - - - - OCIE1B OCIE0B - PCINT[3:0] - ISC11 - - - PRSPI - - - WDE V SP11 SP3 - - - - - RFLB - - WDRF - - - - CPOL - ISC10 - - - PRTIM1 - - - WDP2 N SP10 SP2 - - - - - PGWRT - - BODRF SM[2:0] - - - - CPHA - - - - SPR1 - ISC01 PCIE1 - - PRTIM0 - - CLKPS1 WDP1 Z SP9 SP1 - - - - - PGERS - IVSEL EXTRF - ISC00 PCIE0 - - - - - - - - - OCIE1A OCIE0A - - - - - - - - - TOIE1 TOIE0 - VADC Data Register Low byte - - - - - - - - - - - - - ISC20 - - - - - - - WDCE S SP12 SP4 - - - - - CTPB - PUD OCDRF - - - - - MSTR debugWIRE Data Register - - 98 98 62 63 60 62 34 Fast Oscillator Calibration Register - PRVADC - - CLKPS0 WDP0 C SP8 SP0 - - - - - SPMEN - IVCE PORF SE - 42 34 51 12 15 15 204 80/34 51 41 188 SPI Data Register SPI2X SPR0 109 108 107 26 26 97 97 97 97 CS02 - - - CS01 - - CS00 WGM00 PSRSYNC 22 22 22 EEMPE INT2 INTF2 EEPE INT1 INTF1 EERE INT0 INTF0 23 26 61 61 83 96 General Purpose I/O Register 2 General Purpose I/O Register 1 Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) High Byte Timer/Counter0 (8 Bit) Low Byte - TCW0 TSM - - ICEN0 - - - ICNC0 - - - ICES0 - - - ICS0 - - EEPROM High byte EEPROM Address Register Low Byte EEPROM Data Register - - - - - - EEPM1 - - EEPM0 - - EERIE INT3 INTF3 General Purpose I/O Register 0 10 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB Address 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name PCIFR Reserved Reserved Reserved OSICSR TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTC Reserved PINC PORTB DDRB PINB PORTA DDRA PINA Bit 7 - - - - - - - - - - - - - - - - - - - - - - PORTB7 DDB7 PINB7 - - - Bit 6 - - - - - - - - - - - - - - - - - - - - - - PORTB6 DDB6 PINB6 - - - Bit 5 - - - - - - - - - - - - - - - - - - - PORTC5 - - PORTB5 DDB5 PINB5 - - - Bit 4 - - - - OSISEL0 - - - - - - - - - - - - - - PORTC4 - PINC4 PORTB4 DDB4 PINB4 - - - Bit 3 - - - - - ICF1 ICF0 - - - - - - - - - - - - PORTC3 - PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 Bit 2 - - - - - OCF1B OCF0B - - - - - - - - - - - - PORTC2 - PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 Bit 1 PCIF1 - - - OSIST OCF1A OCF0A - - - - - - - - - - - - PORTC1 - PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 Bit 0 PCIF0 - - - OSIEN TOV1 TOV0 - - - - - - - - - - - - PORTC0 - PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 Page 62 35 98 98 68 68 80 80 80 80 80 80 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega16HVB/32HVB is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 11 8042AS-AVR-09/08 7. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 R1:R0 (Rd x Rr) << BRANCH INSTRUCTIONS 12 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB 7. Instruction Set Summary (Continued) Mnemonics BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN Rd, P Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 k k P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Operands Description Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Flags None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H #Clocks 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT AND BIT-TEST INSTRUCTIONS 13 8042AS-AVR-09/08 7. Instruction Set Summary (Continued) Mnemonics OUT PUSH POP NOP SLEEP WDR BREAK Operands P, Rr Rr Rd Out Port Push Register on Stack Description P Rr STACK Rr Rd STACK Operation Flags None None None None #Clocks 1 2 2 1 1 1 N/A Pop Register from Stack No Operation Sleep Watchdog Reset Break MCU CONTROL INSTRUCTIONS (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None 14 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB 8. Ordering Information -TBD 8.1 ATmega16HVB Speed (MHz) 1 - 8 MHz Power Supply 4 - 25V Ordering Code ATmega16HVB - TBD Package 44X1 Operation Range -30C to 85C Package Type 44X1 44-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) 15 8042AS-AVR-09/08 8.2 ATmega32HVB Speed (MHz) 1 - 8 MHz Power Supply 4 - 25V Ordering Code ATmega32HVB - TBD Package 44X1 Operation Range -30C to 85C Package Type 44X1 44-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) 16 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB 9. Packaging Information 9.1 44X1 32 32 1 1 C C E1 E1 E E End View End View L L 44 44 O O Top View Top View b b A A e e D D Side View Side View A1 A1 SYMBOL SYMBOL A A A1 A1 b b C C D D E1 E1 E E e e L L O O COMMON DIMENSIONS (Unit of Measure = mm) COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOM MIN - - 0.05 0.05 0.17 0.17 0.09 0.09 10.90 10.90 4.30 4.30 6.20 6.20 0.50 0.50 0o 0o NOM - - - - - 11.00 11.00 4.40 4.40 6.40 6.40 0.50 TYP 0.50 TYP 0.60 0.60 - - MAX 1.20 1.20 0.15 0.15 0.27 0.27 0.20 0.20 11.10 11.10 4.50 4.50 6.60 6.60 0.70 0.70 8o 8o NOTE NOTE Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153BE. Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153BE. R R 2325 Orchard Parkway San Orchard 95131 2325Jose, CA Parkway San Jose, CA 95131 TITLE 44X1, 44-lead, 4.4 mm Body Width, Plastic Thin Shrink TITLE Small 44-lead, 4.4 mm Body Width, Plastic Thin Shrink 44X1, Outline Package (TSSOP) Small Outline Package (TSSOP) 5/16/07 5/16/07 DRAWING NO. REV. DRAWING NO. REV. 44X1 A 44X1 A 17 8042AS-AVR-09/08 10. Errata 10.1 10.1.1 ATmega16HVB Rev. A No known errata. 10.2 10.2.1 ATmega32HVB Rev. A No known errata. 18 ATmega16HVB/32HVB 8042AS-AVR-09/08 ATmega16HVB/32HVB 11. Revision history 11.1 Rev.A - 09/08 1. Initial revision 19 8042AS-AVR-09/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2008 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof, AVR (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 8042AS-AVR-09/08 |
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